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High-speed A/D Converter Board

APX-5360

 High-speed A/D conversion board with resolution 12 bit, 1.8 Gsps sampling single-end input 2 ch and capable of recording high-speed signals with high definition.
With various trigger modes, you can acquire necessary data and process data with FPGA. This FPGA realizes digital signal processing function.
Various signal processing functions etc. can be provided and only necessary data can be acquired. With built-in DMA controller, memory transfer is possible without CPU intervention.

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The specification and externals of product are for the improvement and might be changed without previous notice

Features

• PCI Express 2.0 (Gen 2) x 8 enables high-speed data transfer

• DDR3 memory equipped, up to 4 G point size data transferable

• External trigger input · External clock input for each 1 CH

• A maximum of 1.8 Gsps possible AD

• ± 0.5 V Single Ended Input 2 CH

• OFFSET adjustment function

• 4 CH LVTTL level D-IO function (5 V tolerant)

• A-O function of 2 CH

• RoHS compliant

Specifications

Model		APX-5360
Analog I / F	Input	Single end 2 ch (during interleaving: single end 1 ch)
	Input impedance	50 Ω
	Coupling	DC coupling
	Input range	± 0.5 V
	resolution	12 bit
	Sampling rate	Maximum 1.8 Gsps (ns) / Interleave: 3.6 Gsps (ns)
	frequency band	900 MHz - 3 dB
	Input maximum rating	± 2 V (when energized) ± 1.5 V (when energized)
	Analog performance	SFDR: 68.0 dB @ 1800 MSPS, Fin 1 MHz
		SNR: 56.3 dB @ 1800 MSps, Fin 1 MHz
		ENOB: 9.0 bit @ 1800 MSPS, Fin 1 MHz
External clock input		Number of channels: 1
		Signal level: 0.4Vp-p to 1.5Vp-p (sine wave / square wave)
		Frequency: 5 MHz to 100 MHz (when PLL is used)
		150 MHz to 1800 MHz (at the time of direct sampling)
		Input impedance: 1 MΩ / 50 Ω (AC coupling)
		Connector shape: SMA
External trigger input		Number of channels: 1
		Signal level: LVTTL
		Input impedance: 1 KΩ / 50 Ω
		Connector shape: SMA
General purpose port: DIO		Number of channels: DI 4ch DO 4ch
		Signal level: LVTTL
		Connector Model name: HDR - EC 26 LFDT 1 - SLD +
Analog output		Signal level: LVTTL
		Connector Model name: HDR - EC 26 LFDT 1 - SLD +
		Connector shape: SMA
		Number of channels: DI 4ch DO 4ch
Trigger		External trigger / analog trigger / soft trigger
		Analog trigger: Edge pulse
		Trigger position: pre / post delay
Maximum number of samples		2 G words / 2 ch, 4 G words / 1 ch
memory		DDR3-SDRAM (8 GB)
System bus		PCI - Express 2.0 (Gen 2) 5.0 GT / s × 8
Power supply		+ 12 V ± 8%, +12 V / 3.4 A (40.8 W)
Operating environment		Temperature 0 to 50 ° C, humidity 35% to 85% (no condensation)
FPGA		5 GXMA 3 K 1 F 40 I 2 N (manufactured by ALTERA)
External dimensions (not including protrusions)		212.65 mm × 111.15 mm, panel width 20 mm
Supported OS		Windows 7/8, Linux correspond to 32 bit / 64 bit
Environmental response		RoHS

 

Panel

 

Other Document

Block diagram

 

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